1. Field of the Invention
The present invention generally relates to the testing of integrated circuit (IC) devices, and more particularly, to a test board which can test the IC devices operating in either a merged data output mode or a normal standard mode using just one test board.
2. Description of the Related Art
The testing process for IC devices, particularly for memory devices, includes an electrical die sorting (EDS) test, a burn-in test, a reliability test, a final test, and a quality assurance (Q/A) test. The EDS test detects defective elements (chips) on a wafer before the semiconductor assembly processes start. The burn-in test is performed to screen out substandard devices by environmentally (thermally and/or electrically) stressing the packaged devices to accelerate any failures or defects resident in the device. The reliability tests, such as temperature cycling tests (T/C) and pressure cooker tests (PCT), confirm that the IC devices delivered to users are reliable. During the final test all of the DC and AC parameters are checked to confirm that the IC devices achieve the designed performance and functions. The Q/A test is performed on certain of the IC devices that have passed the final test to confirm that the results of the final test are correct.
During the burn-in test, for example, the acceleration of early failures is achieved by thermally and electrically stressing the devices, accompanied by a functional test that measures output signals from the devices. Once the devices are loaded into a test system or test board, they can be exercised or tested under a variety of stresses, whereby their proper function and operation can be verified without removing them from the burn-in test board.
The burn-in test uses test boards where many (e.g., 128) IC devices to be tested are mounted. The test board is then inserted into an oven or a chamber which comprises a temperature controller for subjecting the devices to an increased temperature condition for accelerating their early failure.
For electrically stressing the devices, terminals of the devices are connected in parallel to signal supply pins of a test system, where increased voltage and high current are supplied to the devices. The thermal and electrical stress applications can be performed at one time on all the devices mounted on the test board, even when the number of the input/output (I/O) pins of the test system is limited. However, when performing the functional test portion of the monitor burn-in, the different I/O pins of the test system must be connected to the output terminals of the devices. Accordingly, the burn-in system uses scanning signals for selecting particular devices mounted on the test board, but in the conventional system only one or two devices are selected at the same time by the scanning signals.
The specific number of devices selected is determined by the number of data bits of the output signals from the device and total data input pins of the test system. For example, if the number of data input pins is `m` and the output signals have `a` bits, the maximum number of the selected devices would be `b`, with the relationship m=a.times.b or b=m/a. If only a small number of devices are selected at one time for functional testing, the testing process time increases and the efficiency of the burn-in test decreases.
During the functional testing portion of the burn-in test, after repeatedly writing data according to predetermined test patterns into the memory device, the burn-in tester reads out data from the memory devices via data output terminals (hereinafter referred to as `DQ` terminals). If the data as read from the device is different from the written data, the burn-in tester considers that the device has failed.
For reading data from the memory devices under test, each of I/O pins of a test board on which the devices are mounted must be connected to each of the DQ terminals of the devices. Therefore, when the tester and the test board have a small number of pins, it takes a long time to read out data from the devices mounted on the test board and to test all of the devices.
In order to shorten the testing time, a so-called merged data output test method has been developed. In the merged data output mode, the device delivers its multiple output data through either one or two predetermined DQ terminals, which function as the merged data output terminal or terminals. After writing n-bits of data into the device having n DQ terminals, in which each bit is the same, the tester reads the output data via the merged data output terminal or terminals. If the device has no defective cell, the merged output data will be, e.g., logic `1`, and if the device has a defective cell, the merged output data will be, e.g., logic `0`. Thus, the test can detect that the device under test is acceptable or unacceptable.
However, in the merged data output test method, it is impossible to detect which of the n DQ terminals delivered the false output data. This causes a problem when acceptable module devices are to constructed using the partially defective devices. For example, if a memory device having 8 DQ terminals is found to have just one defective DQ terminal, e.g., DQ 0, this partially defective memory device can be used later to construct a good memory module device. In order to accomplish this, however, it is necessary to know the specific DQ terminal that produced the erroneous data output. Also, in some cases, customers buy these partially defective memory devices at a very steep discount, but they still need to know which specific DQ terminal has failed.
In order to ascertain this failed DQ terminal information, an additional test board and test procedure must be used to detect which DQ terminals deliver the false data. As a result, the cost for the test boards and the required testing time increases.